Reading data from a random access memory (RAM) typically involves accessing a row of memory cells by driving a word line. The word line couples each cell in the row to a pair of bit lines. According to the binary value of the bit stored in each cell, the cell generates a voltage differential across its respective bit line pair. Sense amplifiers coupled to the bit lines amplify the voltage differentials and provide them as outputs on input/output (I/O) lines. The voltages on the I/O lines are further amplified by secondary sense amplifiers, and the resulting signal is latched in an I/O buffer. During a write operation to the RAM, a word line is driven, and a write amplifier drives the I/O lines and selected bit lines to store data in the cells accessed by the driven word line.
In order to increase the speed at which a read or write operation takes place, it is common to precharge and equalize the bit lines and I/O lines prior to a read or write operation. The precharge voltage is typically a voltage intermediate a logic high and logic low of the circuit. This enables the generally capacitive loads of I/O and/or bit lines to charge to a logic high or discharge to a logic low faster than would be possible if the lines had been at one logic level or the other. In addition to being precharged, bit lines and I/O lines are often shorted together, or "equalized" to the precharge voltage. To accomplish the precharge/equalization functions, bit line equalization circuits and I/O equalization circuits are commonly provided. As a result, the critical speed parameters of a memory (the memory cycle) will depend upon the time required for the memory to perform either a read or a write operation (hereinafter referred to as read/write operation) followed by an equalization of the bit lines and I/O lines. Prior art timing schemes initiate an equalization sequence after the read/write sequence by detecting a logic transition at the output of an I/O latch.
Commonly owned, co-pending U.S. patent application Ser. No. 423,822 entitled SYNCHRONOUS STATIC RANDOM ACCESS MEMORY HAVING ASYNCHRONOUS TEST MODE, incorporated by reference herein, sets forth a self-timed static RAM (SRAM) having a synchronous mode of operation in which a read/write timing sequence is followed by an equalization sequence.
Because increasing the operating speed capability of memory devices is a common goal of memory designs, it would be desirable to provide a timing control circuit for a synchronous SRAM that has a shorter timing cycle than prior art approaches.